Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density. One of the difficult factors in the continuing evolution toward smaller device size and higher density has been the ability to consistently form reliable integrated circuit wiring at smaller critical dimensions. For example, the reliability and electrical continuity of integrated circuitry wiring is determined by electrical continuity measurement methods following formation of a metallization level of circuitry wiring, also referred to as acceptance testing (WAT), to quickly determine and correct processing variables that may be causing circuitry defects.
In addition, a recurring problem in etching high aspect ratio openings in dielectric layers in a damascene formation process relates to a failure of the etching process to completely etch through the dielectric layer, also referred to as etch stop behavior. Etch stop behavior has been associated with the build-up of polymer residues at the bottom of an etched opening which overcomes the steady state anisotropic etching process, prematurely stopping the etching depth of the opening. Subsequently formed damascene wiring interconnects are therefore defective and result in open electrical conductive pathways that can no longer be used, thereby detrimentally affecting yield and performance of a multi-level semiconductor device.
There is a continuing need in the semiconductor device manufacturing art for improved wafer acceptance testing (WAT) methods as well as improved damascene formation processes to improve the yield and performance of multi-level semiconductor devices.
It is therefore an object of the invention to provide an improved wafer acceptance testing (WAT) method as well as an improved damascene formation process to improve the yield and performance of multi-level semiconductor devices, in addition to overcoming other shortcomings of the prior art.